CAN 2.0B + AXI4-Lite Core v1.0

Created: 25-05-2025
Contact: support@vyomex.in
License: Project-based (redistribution/sublicensing prohibited)

Overview

The CAN 2.0B + AXI4-Lite Core is a Verilog IP providing a lightweight, synthesizable Controller Area Network (CAN 2.0B) controller wrapped with an AXI4-Lite bus interface. It enables seamless integration into FPGA/SoC platforms, offering standard CAN communication with configurable bit timing, transmit/receive buffers, and protocol-level handling.

Applications

Automotive networks
Industrial automation
IoT devices with CAN support
Embedded controllers & FPGA-based gateways
Test and measurement instruments

Key Features

CAN 2.0B compliant transmitter and receiver
AXI4-Lite wrapper for SoC integration
64-byte address space, 32-bit data bus
Configurable bit timing (BRP, SJW, TSEG1, TSEG2)
Support for Standard (11-bit) and Extended (29-bit) identifiers
Remote and data frame support (RTR, IDE)
Transmit buffer with up to 64-bit payload
Receive buffer with data valid flag
Fully synthesizable RTL, simulation-ready

Architecture

The core consists of two primary layers:

CAN Controller Core – Handles protocol logic, bit timing, transmit/receive operations.
AXI4-Lite Wrapper – Provides host access to registers for configuration, transmit, and receive control.

AXI4-Lite Interfaces & Ports

Port Name	Dir	Width	Description
s_axi_aclk	In	1	AXI4-Lite clock
s_axi_aresetn	In	1	AXI4-Lite reset (active low)
s_axi_awaddr	In	6	Write address
s_axi_awvalid	In	1	Write address valid
s_axi_awready	Out	1	Write address ready
s_axi_wdata	In	32	Write data
s_axi_wvalid	In	1	Write valid
s_axi_wready	Out	1	Write ready
s_axi_bresp	Out	2	Write response
s_axi_bvalid	Out	1	Write response valid
s_axi_bready	In	1	Write response ready
s_axi_araddr	In	6	Read address
s_axi_arvalid	In	1	Read address valid
s_axi_arready	Out	1	Read address ready
s_axi_rdata	Out	32	Read data
s_axi_rresp	Out	2	Read response
s_axi_rvalid	Out	1	Read valid
s_axi_rready	In	1	Read ready
rx	In	1	CAN bus receive line
tx	Out	1	CAN bus transmit line

Register Map (Partial)

Address	Name	Width	Description
0x00	TX_START	1	Start transmission (bit 0)
0x04	STATUS	2	[1]=Busy, [0]=TX Done
0x08	BIT_TIMING1	12	BRP [7:0], SJW [11:8]
0x0C	BIT_TIMING2	8	TSEG1 [3:0], TSEG2 [7:4]
0x10	ID & Frame	32	ID[28:0], IDE, RTR
0x14	DLC	4	Data Length Code
0x18	TX_DATA_LO	32	TX payload lower 32 bits
0x1C	TX_DATA_HI	32	TX payload upper 32 bits
0x20	RX_DATA_LO	32	RX payload lower 32 bits
0x24	RX_DATA_HI	32	RX payload upper 32 bits
0x28	RX_ID	32	RX ID, IDE, RTR
0x2C	RX_STATUS	1	RX data valid flag

Resource Utilization

Resource	Usage
LUTs	416
Flip-Flops	473
Block RAM	0
DSP Slices	0

Note: Resource utilization depends on synthesis tool, target FPGA family, and optimization settings. Reported numbers are indicative for typical configurations.